Staff Post-Silicon DDR Characterization
armChandler (AZ)
Staff Post-Silicon DDR Characterization
Posted today
armChandler (AZ)
SENIORITY
Lead
About the role
Overview:
In this role you drive system-level validation and DDR/LPDDR characterization for Arm SoCs, focusing on memory subsystems across PVT conditions. You will collaborate with cross-functional teams to analyze results, debug issues, and improve silicon performance. You’ll design stress workloads, develop tests, and enable characterization at the system level to support customers bringing products to market. This position offers hands-on impact in optimizing memory performance on next-generation chips within a collaborative, innovation-driven culture. Compensation / Benefits hybrid working salary range disclosed equal opportunities
Responsibilities:
Develop and enable system-level stress workloads on Linux and Bare-Metal environments Collaborate with post-silicon validation to characterize silicon at the system level Debug and resolve system issues and bugs Develop test plans and implement tests for characterizing silicon at the system level
Key requirements:
Experience in pre- or post-silicon validation and characterization with understanding of silicon power, performance, and PVT behavior Experience with DDR/LPDDR architectures including training, calibration, timing, and PHY operation Software skills including C/C++, Arm assembly, Python or scripting languages Experience with voltage/frequency margining and silicon operating limits Experience debugging silicon and system issues using scopes, logic analyzers, debuggers, or similar tools Ability to analyze data, solve complex problems, and communicate technical findings Collaborative teamwork Analytical thinking Strong communication of technical findings DDR/LPDDR architectures (training, calibration, timing, PHY operation) Python automation for characterization and data analysis Low-level C, firmware, hardware control, or silicon debug
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