Hybrid OPC R&D Engineer: Patterning & Tapeout Lead
solidigmSan Jose (CA)
Hybrid OPC R&D Engineer: Patterning & Tapeout Lead
Posted yesterday
solidigmSan Jose (CA)
SENIORITY
Lead
About the role
Solidigm is seeking a Lead OPC R&D Engineer to develop and guide high-quality patterning solutions for memory devices. You will model and correct optical effects, drive SMO and DFM techniques, and ensure the final layout transfers accurately to wafers while meeting manufacturing requirements. In this hybrid US-based role, you will collaborate with design, TD, lithography, and manufacturing teams, mentor colleagues, and contribute to documenting processes and training internal teams.
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.