Senior Physical Design Engineer - 5nm & Synthesis Expert
acl digitalSan Jose (CA)
Senior Physical Design Engineer - 5nm & Synthesis Expert
Posted today
acl digitalSan Jose (CA)
SENIORITY
Senior
About the role
Strong experience in RTL synthesis using Cadence Genus/Fusion compiler, including SDC constraint development and QoR optimization (timing, area, power) Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, MMMC scenarios, OCV, and timing signoff concepts Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure Experience in block-level floorplanning using Cadence Innovus, or fusion compiler including macro placement, IO planning, utilization, Experience in advanced nodes (5nm or below) with ability to work in a fast-paced, execution-driven environment
Before you apply
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Your profile is current
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Two examples you can talk through
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A number in mind
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Your notice period
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