Silicon Design Validation Engineer for FPGA IPs
lattice semiconductorSan Jose (CA)
Silicon Design Validation Engineer for FPGA IPs
Posted today
lattice semiconductorSan Jose (CA)
SENIORITY
Mid
About the role
Lattice Semiconductor in San Jose, CA seeks a Silicon Design Validation Engineer to learn and verify FPGA IP blocks, including SerDes and DDR interfaces, across planning to production. You will develop validation plans, write RTL test logic, run bench tests, and analyze results with statistical tools. This role offers exposure to cutting-edge hardware, software tools, and cross-functional teamwork.
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
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Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.