Senior Silicon Validation Engineer FPGA IP & Testing
lattice semiconductorSan Jose (CA)
Senior Silicon Validation Engineer FPGA IP & Testing
Posted today
lattice semiconductorSan Jose (CA)
SENIORITY
Senior
About the role
Lattice Semiconductor is seeking a seasoned Silicon Design Validation Engineer to drive IP validation from silicon arrival to production release in a fast-paced environment. You will work with SerDes, memory interfaces, and IP blocks, developing robust validation plans and RTL test logic while collaborating across design, verification, and manufacturing teams. The role demands deep expertise in high-speed design, Verilog/VHDL, FPGA development tools, and automation using Python or similar
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.