Senior Silicon Circuit Validation Engineer
Senior Silicon Circuit Validation Engineer
Posted yesterday
SENIORITY
Lead
About the role
- Own the co-design, bring-up, and post-silicon validation of the analog, digital, and mixed-signal circuits that underpin NVIDIA's safety, security, reliability, and performance enhancement features — across the full PVT space, from first power-on through production sign-off.
- Close the simulation-to-silicon gap. Build methodologies that correlate measured circuit behavior against pre-silicon predictions, quantify where the model diverges from reality, and produce analysis that design and architecture teams can act on with confidence.
- Trace failures to their source — a circuit marginality, a power integrity interaction, a process corner the model didn't anticipate, or a system-level coupling — and drive the resolution all the way through to confirmation.
- Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing rigor. Know where AI accelerates real work and where it introduces risk.
- Build the tools your work depends on. Design and own automation and analysis infrastructure that lets you execute efficiently across multiple products simultaneously without sacrificing depth or coverage.
- Sit at the decision table. Your data drives binning strategy, guard-band decisions, reliability sign-off, and design improvements for future programs. When the data is ambiguous, your analysis is what resolves it.
- Lead and mentor junior engineers and interns. Raise the technical floor of the team around you.
- What we need to see:
- BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience in the lab.8+ years of hands-on silicon bring-up, frequency and power characterization, or post-silicon validation on real hardware.
- Strong circuit fundamentals — analog, digital, and mixed-signal — with the intuition to know what you're measuring and why it matters.
- Hands-on lab depth: oscilloscopes, multimeters, DAQs, spectrum analyzers, and silicon debug tools. Comfort with tester-to-system correlation.
- Depth in product binning, PVT analysis, guard-banding, and optimization trade-offs. Enough statistical fluency to know when a distribution is telling you something.
- Exposure to critical path analysis, power integrity, dI/dt and PDN analysis, transistor physics, and silicon reliability and aging mechanisms.
- Scripting proficiency in Python, C/C++, or equivalent. You build the infrastructure your characterization depends on.
- Ways to stand out from the crowd:
- You've built a co-design or correlation methodology precise enough that other teams adopted it.
- Traced a silicon anomaly — a noise issue, a margin failure, a feature that didn't hold across corners — to its root cause and driven the fix all the way through to closure.
- Built or deployed AI-driven flows for circuit analysis or failure triage, and can speak to both the outcome and the guardrails you put in place.
- Led or mentored engineers and made them measurably better at the craft.
- Experience on datacenter-scale or high-performance silicon, where complexity raises the cost of being wrong and the standard for rigor is correspondingly higher.
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