Staff ASIC/SoC Design Engineer - RTL & Microarchitecture

Location: Santa Clara, CA Candidates must currently reside in California

Schedule: Full-Time M-F, 4 days onsite

Compensation: $195,000 - $226,000 base salary. Base salary is determined based on location, experience, and the pay of employees in similar positions. Compensation package also includes new-hire RSU grants, the opportunity for annual RSU grants, and highly competitive benefits.

About the Company: Our client is a leading fabless semiconductor company at the forefront of edge AI-based computer vision. Their SoCs (Systems-on-Chips) power applications ranging from autonomous driving and ADAS to intelligent video security and robotics. They are building the next generation of Edge AI, operating at the intersection of high-performance hardware and real-world software deployment.

The Opportunity: This is an ideal opportunity for an experienced VLSI/ASIC designer who wants broad technical exposure and meaningful ownership of the chip being built. Rather than focusing on a narrow block or isolated function, this position provides exposure across video compression, image processing, vector computation, processor cores, memory subsystems, and flexible compute architectures for next-generation edge AI applications. We are particularly interested in candidates with hands-on RTL design experience developing complex IPs or significant SoC subsystems, such as AI accelerators, vector processors, RISC-V CPUs, advanced image processing pipelines, HEVC/AV1 video codecs, or LPDDR5/LPDDR6 memory subsystems. You will have the opportunity to influence microarchitecture, optimize RTL for performance, power, and area, participate in chip bring-up, and see your work progress from concept through silicon.

Responsibilities: Design and implement video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference. Work with processor cores and memory subsystems using SystemVerilog, with a focus on next-generation edge AI applications including automation, robotics, and intelligent low-power embedded systems. Design and implement complex ASIC/SoC IPs and significant subsystems, taking ownership of RTL development and contributing to microarchitecture decisions. Perform logic design, implementation, and verification using Verilog, SystemVerilog, and required programming and scripting languages. Synthesize and optimize RTL for timing, area, and power. Explore microarchitecture and architectural tradeoffs through rapid modeling using scripting languages such as Python and Perl. Develop front-end methodologies and tool flows. Participate in chip bring-up and testing. Analyze code coverage and functional coverage and provide recommendations to the verification team to address coverage gaps.

Requirements: Master's degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, with 5-10 years of experience. Good understanding of computer architecture, logic design, and VLSI design. Hands-on experience designing and implementing complex ASIC/SoC IPs or subsystems using RTL.Experience with one or more of the following is highly desirable: AI accelerators, vector processors, RISC-V CPUs, advanced image processing pipelines, HEVC/AV1 video codecs, or LPDDR5/LPDDR6 memory subsystems. Knowledge of SystemVerilog, Verilog, Python, and Perl. Knowledge of design verification and functional coverage. Ability to program in scripting languages and write assembly-language programs. Strong communication, collaboration, and problem-solving skills. Knowledge of logic synthesis and timing closure is preferred. Experience developing microarchitecture for complex IPs or SoC subsystems is a strong plus.