Senior FPGA Engineer
cisco systemsSan Jose (CA)
About the role
Overview:
In this role, you will own FPGA-related work from concept to production, focusing on high-performance data-center switching hardware. You will collaborate with system designers and verification teams to ensure robust, high-quality products that meet industry standards. You’ll tackle RTL design, synthesis, timing closure, and hardware debugging to enable next-generation Cisco solutions. This is a hands-on, cross-functional role at the intersection of hardware and AI-scale systems. You will contribute to shaping Cisco’s FPGA-driven platforms. Compensation / Benefits medical, dental and vision insurance 401(k) with Cisco matching paid parental leave paid holidays and vacation time sick time off stock grants (RSUs) eligibility
Responsibilities:
Full-lifecycle FPGA design and RTL development (Verilog/SystemVerilog) Synthesis, timing closure, and timing constraints Simulation, verification, and test bench development Hardware lab debugging and diagnostics Cross-functional collaboration with system designers, diagnostics engineers, and vendors Independent work with minimal guidance
Key requirements:
Bachelor’s degree in electrical engineering with 7+ years of experience or Master’s degree in electrical engineering with 4+ years of experience Experience in full-lifecycle FPGA design Experience writing structured, reusable Verilog Experience with vendor toolchains (Vivado, Quartus, Libero) Experience with timing closure and timing constraints Lab experience with oscilloscopes and logic analyzers Self-motivated with minimal guidance Cross-functional collaboration Problem-solving and debugging ability Verilog/SystemVerilog RTL development FPGA architecture and synthesis Timing closure and timing constraints
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