Senior Staff FPGA Clocking & PLL Design Engineer
advanced micro devicesSan Jose (CA)
Senior Staff FPGA Clocking & PLL Design Engineer
Posted today
advanced micro devicesSan Jose (CA)
SENIORITY
Lead
About the role
AMD is seeking a Staff Design Engineer to lead PLL design and integration for FPGA products. You will work across process nodes, guiding analog/mixed-signal IPs and PLL topologies while collaborating with cross-functional teams to optimize performance and reliability. You will contribute to post-silicon validation, system-level simulations, and lab bring-up, leveraging Vivado tools to validate clocking solutions in cutting-edge SoCs.
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