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Principal Analog IC Design Engineer, High Speed SerDes

Posted today

cadenceSan Jose (CA)

SENIORITY

Lead

SALARY

$136,500 per year

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About the role

Principal Analog IC Designer The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. Candidate's background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development. Working knowledge of a set of common SerDes standards and their electrical requirements is a plus. Must have a thorough understanding of jitter and signal equalization techniques. Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators. Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment. Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification. Cadence tool experience, lab test experience, and design experience at >10 Gbps and in

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