Principal ESD Engineer

Responsibilities: Lead ESD architecture development for advanced-node semiconductor products Design and optimize custom ESD protection devices, clamps, and ESD IP solutions Provide co-design support to maximize performance and ESD robustness Lead ESD sign-off reviews and risk assessments for complex SoCs and mixed-signal products Develop and maintain automated ESD verification methodologies and flows Support silicon characterization using HBM, CDM, TLP, VF-TLP, and Latch-Up testing Drive root-cause analysis of ESD-related failures and implement corrective actions Collaborate with foundries, EDA vendors, and internal design teams

Key requirements: M.S. in Electrical Engineering or related field 10+ years of semiconductor ESD design experience Strong knowledge of ESD device physics, HBM, CDM, TLP, VF-TLP, Latch-Up, Advanced CMOS and FinFET technologies Hands-on experience with ESD protection design for FinFET SoCs and SerDes products Hands-on experience in ESD cell design and custom ESD IP development Strong knowledge of ESD sign-off methodologies and verification techniques Experience with Calibre PERC or equivalent ESD verification tools Proven ability to develop and deploy ESD methodologies across multiple product families and technology nodes Demonstrated leadership in cross-functional engineering environments Strong initiative, collaboration, and ownership with track record of delivering under deadlines Strong technical writing and communication skills across global teams collaboration leadership ownership ESD device physics HBM CDM