SoC Physical Design Architect - Tapeout Lead
astera labsSan Jose (CA)
SoC Physical Design Architect - Tapeout Lead
Posted yesterday
astera labsSan Jose (CA)
SENIORITY
Lead
About the role
Astera Labs in San Jose, CA, is seeking a Principal Physical Design Engineer to own RTL2GDS for high-performance connectivity SoCs, driving floorplan, timing, power, and signoff from RTL to tapeout. You will lead physical design methodology, mentor engineers, and collaborate with RTL, DFT, analog, and package teams to deliver next-generation silicon on 7nm or below nodes, with full-chip signoff and tapeout support.
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