Design Verification Engineer
infotree global solutionsSanta Clara (CA)
$129,800 - $212,800 per year
Apply (opens in a new tab)Design Verification Engineer
Posted yesterday
infotree global solutionsSanta Clara (CA)
SENIORITY
Lead
SALARY
$129,800 - $212,800 per year
About the role
Get AI-powered advice on this job and more exclusive features. You can get further details about the nature of this opening, and what is expected from applicants, by reading the below. Infotree Global Solutions provided pay range This range is provided by Infotree Global Solutions. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range$80.00/hr - $90.00/hrDirect message the job poster from Infotree Global Solutions We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve client's abilities to deliver the highest quality, industry-leading technologies to market. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. THE PERSON:You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Develop/Maintain tests for functional verification. Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. Work on functional & code coverage verification. Provide technical support to other teamsPREFERRED EXPERIENCE:Experience with C/C++Experience with Verilog, System Verilog, and modern verification libraries like UVM10+years of ASIC design verification experience Experience / Background with DDR or Memory Controller. PHY Verification is a plus Experience with scripting languages like Python, Perl and TCL is a plus. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Understanding of Design for Test methodologies and DFT verification experience is a plus Proficient in debugging firmware and RTL code using simulation toolsACADEMIC CREDENTIALS: • Bachelor's or master's degree in computer engineering/Electrical Engineering Seniority level Seniority level Not Applicable Employment type Employment type ContractJob function IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Infotree Global Solutions by 2xSign in to set job alerts for "Design Verification Engineer" roles. Cupertino, CA $129,800.00-$212,800.00 2 weeks agoSunnyvale, CA $114,000.00-$166,000.00 2 weeks agoSan Jose, CA $136,000.00-$204,000.00 5 days agoSunnyvale, CA $114,000.00-$166,000.00 2 weeks ago Design Verification Engineer at Santa Clara, CA (Onsite) xmcpwfu Mountain View, CA $107,900.00-$242,000.00 3 weeks ago Physical Design and Verification Engineer Santa Clara, CA $97,700.00-$182,624.00 2 days agoSunnyvale, CA $142,000.00-$203,000.00 2 weeks ago Mountain View, CA $107,900.00-$242,000.00 1 week agoSunnyvale, CA $173,000.00-$249,000.00 2 weeks agoSan Jose, CA $140,000.00-$160,000.00 1 month agoSanta Clara, CA $161,250.00-$260,000.00 6 months agoASIC Design Verification Engineer, Devices and Services Mountain View, CA $156,000.00-$229, hours agoSanta Clara, CA $96,000.00-$184,000.00 6 days agoSan Jose, CA $129,400.00-$177,900.00 4 days agoSanta Clara, CA $108,000.00-$212,750.00 6 days ago Advanced Physical Design and Verification Engineer (7036) San Jose, CA $85,500.00-$134,000.00 1 day agoSan Jose, CA $130,000.00-$192,000.00 5 days ago We're unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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