Compute Subsystem Architect
$211,000- $356,000
Apply (opens in a new tab)Compute Subsystem Architect
Posted 48 days ago
SENIORITY
Lead
SALARY
$211,000- $356,000
About the role
- Architect compute subsystems (CPU cluster, L2/L3/SLC cache, coherent meshfabric) for next-generation ASIC and advanced Arm computing platform products.* Own CMN topology recommendations: mesh dimension, HN-F/SN-F/RN-F placement, SLC distribution, snoop filter policy, and QoS parameters.* Build CPU subsystem performance models to quantify many-core scaling: latency, bandwidth-per-core, and mesh congestion under AI-era workload traffic patterns.* Drive technology readiness: track Arm Neoverse CSS/CMN roadmap, identify IPgaps, and lead technical engagement with Arm on architecture and multi-die scope.* Evaluate architectural implications of 3D-IC and chiplet splits on CMN topology, CHI credit return, and snoop timing; hand off quantified constraints topackaging and physical teams; co-design while maintaining focus on computing architecture.* Align design with potential product landing vehicles including custom ASICsolutions and advanced Arm platforms (including future CPU Dielet configurations).* Prepare architecture specifications and technical documents; present trade-offsto engineering leadership and executives.#LI-WC2Main Requirements and Qualifications
- Deep expertise in Arm CMN-series coherent mesh networks: topology sizing, HN/SN/RN placement, SLC optimization, QoS. Arm Neoverse CSS experience strongly preferred (required).* Proficiency in AMBA CHI protocol: transaction types, snoop behavior, credit flow, and debug mechanisms (required).* Experience architecting for many-core scaling (32+ cores): coherency overhead, cache/fabric co-optimization, tail-latency analysis (required).* Familiarity with CXL Type-1/2/3 and server-class RAS architecture (desired).* Excellent communication skills; ability to produce high-quality architecture documents and present complex trade-offs to both engineers and executives.* Educational background: MS in Electrical Engineering, Computer Engineering, Computer Science* Minimum 10 years of relevant industry experience. Scope* Architecture definition and technology readiness for Neoverse CSS-based compute subsystems: CPU cluster, CMN, cache/SLC, and CHI coherency.* Architectural interface ownership for chiplet/3D-IC configurations; packaging and D2D implementation handled by dedicated functional teams.* Opportunity to shape MediaTek's advanced computing platform strategy and data center CPU roadmap from the ground up.
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