FPGA Design Engineer (Verilog)

Job Title: FPGA Design Engineer (Verilog) Duration: 6 months assignment Shift Timing (Day/ Evening/ Night): First Shift (8 am to 4:30 pm) Job Description: The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families. Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required.Required Skills:5+ years of FPGA and/or ASIC design experience; Strong Xilinx/AMD Vivado experience; Experience with Versal family devices; Verilog/SystemVerilog HDL proficiency required; Advanced FPGA implementation skills (synthesis, timing closure, constraints); Active U.S. security clearance Preferred Skills: 2+ years of FPGA design experience; Strong Xilinx/AMD Vivado experience; Verilog/SystemVerilog proficiency; Advanced FPGA implementation skills (synthesis, timing closure, constraints); Required Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.