Senior SoC/ASIC Physical Design Engineer

Responsibilities: Build modern physical design flows using EDA tool fusion and machine learning to optimize PPA, resources, and accelerate time-to-closure. Perform synthesis, floorplanning, PDN generation, place & route, timing, noise, verification, EM/IR checks, and signoff. Create and refine PD methodologies and automation scripts to streamline design and signoff processes. Partner with RTL, DFT, and ASIC teams to define architectural feasibility, timing/power/area targets, and design trade-offs. Apply a metrics-driven approach to resolve design and timing challenges and ensure predictable milestone delivery. Lead closure activities, including STA, noise analysis, logic equivalency, physical verification, and power integrity (EM/IR).

Qualifications: Bachelor’s in Electrical Engineering, Computer Engineering, or Computer Science .Master’s preferred At least 10 years of experience in ASIC/SoC physical design and flow development. Expertise in RTL-to-GDSII design flows, Synopsys EDA tools, and advanced PD methodologies like synthesis, place & route, STA, CDC, power analysis. Knowledge of FinFET/deep sub-micron CMOS, DFT methodologies like Scan, MBIST, LBIST and power/IR drop management. Strong ability to analyze design parameters and QoR metrics and implement advanced power optimization techniques such as SVS, DVFS, and SRAM split-rail architectures. Proficient in Python, Tcl, Perl, bash/csh, and automation scripting. Strong analytical and problem solving skills with proven ability to lead design closure and collaborate across teams.