Senior Physical Design Engineer
Senior Physical Design Engineer
Posted yesterday
SENIORITY
Lead
About the role
- Lead and implement physical design for chips across process nodes ranging from 40nmto 7nm
- Perform block-level and top-level physical implementation
- Drive floorplanning activities including multi-power domain design, power grid (PG)planning, block shaping, and clock tree implementation
- Interface with internal and external stakeholders, including Design, IP, and Library teams
- Conduct physical verification at block and chip level
- Perform static and dynamic IR drop analysis, as well as signal and powerelectromigration (EM) checks
- Develop methodologies and flows for physical design and timing closure
- Collaborate with Synthesis, STA, and RTL design teams to meet physicalimplementation and power intent requirements
- Support ESD, IO padring, and analog integration; experience with packaging types suchas flip-chip and WLCSP is preferred
- Bachelor’s degree in Electrical Engineering with 8+ years of experience, OR Master’sdegree in Electrical Engineering with 10+ years of experience
- Multiple tapeout experience
- Extensive hands-on experience with tools such as Innovus, VCLP, Formality, LEC, Calibre, and timing closure tools
- Strong expertise with Cadence Innovus (required)
- TCL scripting experience (required); Python is a plus
- Knowledge of physical design flows and methodologies
Before you apply
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A number in mind
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Your notice period
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Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
