FPGA Functional Safety Engineer RTL & ISO
tensor autoSan Jose (CA)
FPGA Functional Safety Engineer RTL & ISO
Posted today
tensor autoSan Jose (CA)
SENIORITY
Lead
About the role
Tensor is seeking an experienced FPGA Safety Engineer to analyze and enhance safety for FPGA subsystems, ensure compliance with ISO 26262, and drive RTL design and verification across complex DSP-enabled FPGA pipelines. The role requires 5+ years in FPGA development, Verilog/SystemVerilog proficiency, and hands-on experience with Xilinx toolchains and CPUs on Zynq platforms. Strong scripting and HDL skills are essential for this position in San Jose.
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