Overview:
In this DFT role you will implement and integrate DFT features across RTL to tapeout for AI/ML architectures. You’ll work with a cross‑functional ASIC team to reduce test cost while preserving high coverage and to enable efficient debug and yield learning. The position offers collaboration across design, PD, verification, and test groups in a hybrid setup in Santa Clara, Austin, or Fort Collins. This is a senior/entry to senior role, with level determined during interviews, focused on shaping robust test flows for cutting‑edge chips. Compensation / Benefits competitive compensation package benefits equal opportunity employer hybrid work model
Responsibilities:
Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs Own ATPG, test coverage analysis, and gate‑level simulation (Synopsys VCS/Verdi) to sustain high quality test coverage Plan, implement, and verify MBIST; collaborate with Test Engineering on test planning, pattern delivery, and debug Develop and refine DFx flows that integrate with front‑end and physical design flows, balancing coverage, cost, and intrusiveness Work with cross‑functional teams to ensure design, verification, and production test readiness
Key requirements:
BS/MS/PhD in EE/ECE/CE/CS with 5+ years in advanced DFx/DFT for complex ASIC/SoC designs Fluent in Verilog RTL for DFT logic (lock‑up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM Hands‑on experience with ATPG and DFx insertion tools, fault models (Stuck‑at, Transition, Path Delay, IDDQ, Cell‑Aware) Experience with low‑power design flows Strong debug and problem‑solving skills across design hierarchies; collaborative with design, PD, verification, and test teams collaboration across cross‑functional teams strong debugging and problem‑solving proactive communication Verilog RTL for DFT SystemVerilog/UVM ATPG