Senior ASIC Formal Verification Engineer
us health partnersBrooklyn (NY)
Senior ASIC Formal Verification Engineer
Posted today
us health partnersBrooklyn (NY)
SENIORITY
Lead
About the role
Etched seeks a Formal Verification Engineer to advance verification across ASIC DV, interface IP, and SoC subsystems powering our ASICs. You will drive formal properties, enable proof convergence, and collaborate with architects, RTL designers, DV, emulation, software and firmware teams to prove design correctness and minimize corner-case bugs.
Expect to build reusable formal environments, employ SystemVerilog Assertions, and align verification with simulation and regression.
Before you apply
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Your profile is current
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Two examples you can talk through
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A number in mind
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Your notice period
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Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
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