Senior SRAM Layout Architect - CMOS 5nm/3nm

Posted today

dgn technologiesSanta Clara (CA)

Electronics Engineers, Except Computer Semiconductor and Related Device Manufacturing

SENIORITY

Senior

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About the role

DGN Technologies is seeking an experienced layout engineer to lead custom IC layout for SRAM and memory IP in advanced CMOS nodes. You will own floorplanning, routing, and top-level verification in collaboration with circuit, CAD, and foundry teams. You will mentor engineers, advance layout methodologies, and ensure memory IP delivery meets tight reliability and performance targets in cutting-edge process nodes (5nm/3nm and below).

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