System-Level Memory Validation Engineer (DDR/LPDDR/HBM)

Posted yesterday

synopsysNew York (NY)

Validation Engineers Electronic Computer Manufacturing

SENIORITY

Lead

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About the role

Synopsys is seeking a System Level Test Engineer to own system-level silicon validation of DDR, LPDDR, and HBM memory interface IP in the lab. You will bring up silicon, validate timing across DRAM and HBM devices, and characterize margins at speed. This hands-on role requires proficiency with oscilloscopes, protocol analyzers, and automation with Gitlab to scale validation across product generations. You will collaborate with firmware and design teams to ensure IP readiness for production.

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