ASIC Design Verification Engineer

Location: Remote

Job Type: W2 Contract

Duration: 9-12 Months (Extension Possible)

Job Description: We are seeking experienced ASIC Design Verification Engineers with strong hands-on experience in System Verilog and UVM-based verification. Candidates will work on subsystem and full-chip integration verification for complex semiconductor designs. Required Technical Skills Strong experience in ASIC Design Verification (DV). Hands-on experience with System Verilog and UVM. Experience in subsystem and full-chip integration verification. Strong understanding of AXI protocols and bus interfaces. Experience with PCIe verification. Experience with Ethernet protocol verification. Knowledge of HBM (High Bandwidth Memory) architecture and verification. Experience with Die-to-Die (D2D) interconnect verification. Strong debugging and functional verification skills. Experience developing and maintaining UVM testbenches, sequences, drivers, monitors, and scoreboards.

Key Responsibilities: Develop and execute UVM-based verification environments. Perform subsystem and full-chip integration verification. Verify complex interfaces including AXI, PCIe, Ethernet, HBM, and Die-to-Die. Develop test plans, test scenarios, and functional coverage. Debug simulation failures and collaborate with design teams. Ensure design functionality meets verification requirements.