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Design Verification Engineer - Hardware for High-Perf Silicon

Posted today

river aiPalo Alto (CA)

SENIORITY

Lead

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About the role

River AI is seeking exception design verification engineers to ensure our high-performance custom silicon is functionally correct. Based in Austin, TX or Palo Alto, CA, you will define test benches and verification environments across simulation, formal, and emulation, collaborating with RTL, performance modeling, and compiler teams. You will develop scalable UVM test benches, constrained-random sequences, and coverage models, while debugging issues to accelerate silicon bring-up and

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