Senior ASIC Physical Design Engineer – PPA & Tapeout
matxMountain View (CA)
Senior ASIC Physical Design Engineer – PPA & Tapeout
Posted yesterday
matxMountain View (CA)
Electronics Engineers, Except ComputerResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)
SENIORITY
Lead
About the role
MatX Inc. in Mountain View, CA, is seeking silicon physical design engineers to develop high-performance, power-efficient silicon for GenAI. You will own subsystems and drive PD from RTL to tapeout, ensuring scalable, correct implementations.
The role requires BS in Electrical Engineering and 8+ years of ASIC PD experience, with strong Python/TCL/Perl skills and collaboration with Design/DFT teams to optimize performance, power, and area.
Before you apply
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A number in mind
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