Principal Digital Engineer (DFT Design)
renesas electronics americaChandler (AZ)
Principal Digital Engineer (DFT Design)
Posted today
renesas electronics americaChandler (AZ)
SENIORITY
Lead
About the role
Overview:
Join Renesas' automotive PMIC team to design advanced power-management ICs that power tomorrow’s vehicles. You will contribute across the digital design flow, from specification to test and validation, collaborating with cross-functional teams to meet ASIL-B/D requirements. You’ll drive testability through DFT/Scan insertion, ATPG, and RTL enhancements, shaping scalable, reliable automotive silicon. This role offers hands-on design work, opportunity to influence patterns and tests, and a clear path to impact in a growing automotive business. You will work on-site three days a week and play a key part in delivering high-quality automotive PMIC solutions. Compensation / Benefits competitive benefits package salary on-site work arrangement opportunity to work on world-leading automotive PMICs
Responsibilities:
Insert DFT/Scan in digital logic and ATPG; validate test patterns on pre/post layout gate level netlist Deliver test patterns to TEST engineering and validate on silicon Insert Logicbist with standard industry tools and improve scan coverage Modify RTL for scan and reduce ATE tester time while maintaining coverage Participate in digital design flow (RTL Verilog/SystemVerilog, timing constraints, synthesis, P&R coordination, timing analysis, lint, CDC) Collaborate with Architects, Design, P&R, Test and Silicon validation teams Assist with top-level test-bench creation and gate-level simulations Debug scan pattern failures on ATE and fix patterns Write design docs and DFT specifications; lead design reviews and checklists On-site presence required three days a week
Key requirements:
Masters plus 12+ years or Bachelors plus 15+ years in digital design and DFT Strong DFT fundamentals; hands-on scan insertion, ATPG, and Logicbist insertion Gate-level simulations and pattern delivery to test engineering; pattern validation Basic digital RTL coding in addition to synthesis exposure Experience with at least 8 tapeouts and DFT/Scan Knowledge of synthesizable design, timing constraints Experience with industry tools Synopsys, Cadence, Mentor, Siemens; Tetramax a plus Excellent written and verbal cross-functional communication; analytical mindset team player with independent thinking attention to detail and accuracy analytical mindset and openness to new ideas Scan insertion ATPG Logicbist insertion
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