RTL Integration Engineer | SoC Debug & CDC Expert
RTL Integration Engineer | SoC Debug & CDC Expert
Posted yesterday
SENIORITY
Lead
About the role
- CDC/RDC analysis for RTL and gate-level designs, plus synthesis, palladium modeling and STA support.
- Candidates should have expertise in UVM and System
- Verilog, GLS, zero-delay and SDF simulations, and strong debugging and communication skills. A Bachelor's degree with 12+ years experience is required.
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
