MTS - Design Verification

About the Role: We're looking for experienced Design Verification Engineers to take ownership of verifying complex IP, subsystems, and full-chip functionality for a cutting-edge AI accelerator. This is a highly technical individual contributor role where you'll work alongside architecture, RTL, and software teams to ensure first-pass silicon success while helping establish scalable verification methodologies for future products.

What You'll Do: Own verification for a major functional area based on your technical expertise. Define and execute comprehensive verification strategies spanning IP, subsystem, SoC, and emulation environments. Build and enhance AI-assisted verification workflows to improve productivity and reduce verification cycle times. Develop reusable UVM-based verification environments, test plans, stimulus, and coverage models. Drive functional closure by debugging complex design issues and collaborating closely with design and architecture teams. Contribute to verification methodology improvements as the organization scales future silicon programs.

What We're Looking For: 5+ years of hands-on pre-silicon verification experience on complex ASIC or SoC programs. Strong experience in one or more of the following: Block or subsystem verification CPU subsystem or IP integration Full-chip/SoC verification Hardware emulation DMA or Network-on-Chip (NoC) verification Functional debug and coverage closure on complex designs Demonstrated ownership of verification from planning through functional coverage closure. Deep understanding of UVM methodology, constrained-random verification, and scalable testbench architecture. Strong ability to interpret hardware and software specifications and translate them into effective verification strategies. Passion for improving verification efficiency through automation and AI-assisted development workflows. Excellent collaboration skills with the ability to thrive in a fast-moving startup environment and contribute across multiple verification domains. Experience setting priorities and delivering against aggressive development schedules.

Nice to Have: Experience with RISC-V architectures. Hardware emulation platforms such as Cadence Palladium, Siemens Veloce, or similar. Post-silicon validation or bring-up experience. Compensation is competitive and will be determined based on experience, technical expertise, and location. In addition to base salary, the package includes meaningful equity participation, comprehensive medical, dental, and vision coverage, a 401(k), and generous paid time off.