Senior ASIC Design Engineer RTL, Timing & Tapeouts
upscale aiBrooklyn (NY)
Senior ASIC Design Engineer RTL, Timing & Tapeouts
Posted today
upscale aiBrooklyn (NY)
SENIORITY
Lead
About the role
Upscale, Inc. is building high-performance AI infrastructure with a strong focus on silicon, systems, and networking. We seek a senior ASIC design engineer to define micro-architecture and deliver RTL that meets power, performance, and area targets.
You will collaborate with architecture, verification, physical design, and DFT teams to drive design fixes and ensure robust tapeouts in a fast-paced startup environment. The role requires strong Sys Verilog expertise and 5+ years in ASIC logic design.
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