STA Engineer

Key Responsibilities: Perform block-level and full-chip STA across the project lifecycle, from early investigation to final tapeout. Execute RTL synthesis flows, ensuring optimal QoR (Quality of Results) and alignment with timing constraints. Write and develop timing constraints (SDC) for PCIe and other high-speed interfaces. Build and enhance timing methodology and infrastructure to support flows from synthesis to implementation and closure. Collaborate with architects and logic designers to generate accurate block and chip-level timing constraints. Define analysis scenarios and margining strategies with system and technology teams. Partner with physical design teams to achieve timing closure and ensure robust silicon sign-off.

Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.5+ years of industry experience, with at least 3 years focused on STA and synthesis/timing closure. Hands-on expertise with Synopsys Prime Time (STA) and Design Compiler/Fusion Compiler (synthesis), or equivalent tools. Proven experience writing and debugging timing constraints (SDC) for PCIe or other high-speed protocols. Strong collaboration skills with physical design and architecture teams.

Preferred Qualifications: Experience with multi-clock domain designs, CDC analysis, and power-aware STA.Familiarity with advanced process nodes (7nm and below).Knowledge of timing ECO flows and sign-off methodologies. Exposure to high-speed interfaces (PCIe, DDR, Ser Des) and their timing requirements.