RISC-V Post-Silicon Validation Engineer
tenstorrent universitySanta Clara (CA)
RISC-V Post-Silicon Validation Engineer
Posted yesterday
tenstorrent universitySanta Clara (CA)
SENIORITY
Lead
About the role
Tenstorrent is seeking a Post-Silicon Validation Engineer to drive bring-up, validation, and debugging of RISC-V based SoCs. The role sits at the intersection of silicon, firmware, and system software, requiring hands-on lab experience and deep understanding of SoC architectures. The position is hybrid, based out of Austin TX or Santa Clara CA, with opportunities at various experience levels and compensation aligned with the level and location.
Before you apply
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A number in mind
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Your notice period
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