Senior Staff Engineer, ASIC Design/Implementation — LEC/STA/Power Analysis

Responsibilities: Develop and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes and constraints for STA signoff. Own and contribute to STA-related tasks, including timing ECOs for blocks and SoCs, and developing custom scripts for flow management. Perform static timing analysis (STA) using industry-standard tools like Primetime. Define and implement timing signoff methodologies, including process corners and uncertainties. Resolve tool issues independently or with EDA tool vendors. Conduct post-route timing checks and quality of results (QoR) analysis. Automate STA processes using scripting languages such as Tcl or Python. Create QoR dashboards and histograms for STA runs across all modes. Ensure compliance with timing signoff checklists and criteria. Document best practices and lessons learned for continuous improvement.

Qualifications: Bachelor's degree in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience, or a Master's/PhD with 3-5 years of experience. Minimum of 5 years of industry experience in ASIC timing and STA.Strong understanding of ASIC design flows from RTL to GDSII.