Principal Silicon Design Verification Engineer
microsoftSanta Clara (CA)
Principal Silicon Design Verification Engineer
Posted today
microsoftSanta Clara (CA)
SENIORITY
Lead
About the role
Overview:
In this role you will lead validation of DPU silicon for datacenter scale, partnering with architecture and cross-functional teams to ensure robust pre- and post-silicon validation. You’ll shape test plans, implement UVM-based verification, and drive efficient validation methodologies. The position offers high visibility and impact, with opportunities to mentor others and influence next-generation designs. You will work on diverse domains within a critical cloud hardware program that powers Microsoft’s Intelligent Cloud mission.
Responsibilities:
Lead functional validation of complex ASIC/SoC using UVM-based test benches Define pre-silicon verification strategies and post-silicon validation plans Collaborate with architecture, design, verification, and partner teams for project execution Develop test plans, tests in C, and infrastructure to complete functional validation Run tests, debug failures, and create stress/performance scenarios to meet goals Assist chip bring-up and write test firmware to support multiple teams Innovate validation methodologies and tooling to improve efficiency Coach and mentor engineers in areas of expertise
Key requirements:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years of experience OR Master's in same fields AND 6+ years OR Bachelor's in same fields AND 8+ years OR equivalent experience Ability to pass Microsoft Cloud Background Check and security screenings Collaborative mindset Growth mindset Adaptability UVM verification methodology Verilog SystemVerilog
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