Senior SoC Verification Engineer - UVM & SystemVerilog
techdigital groupMidland (TX)
Senior SoC Verification Engineer - UVM & SystemVerilog
Posted today
techdigital groupMidland (TX)
SENIORITY
Lead
About the role
TechDigital Group seeks an experienced ASIC Verification Engineer to own end-to-end verification across multiple design blocks. You will develop and maintain testbenches, sequences, agents, and scoreboards using SystemVerilog and UVM from scratch.
You will execute directed and constrained tests, debug deeply, and drive coverage closure for complex networking silicon and interconnect ASICs. Strong collaboration with customer teams is essential.
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
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