Full Stack Engineer
intersourcesSaratoga (CA)
About the role
ME/BE with a minimum of 8-15 years of experience.
Hands-on knowledge of SystemVerilog and Verilog is mandatory.
Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
Proven expertise in designing and optimizing scheduling and QoS mechanisms.
Experience with Ethernet and IP protocols.
Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.