Senior Memory IP Design Architect
cadence design systemsSan Jose (CA)
About the role
Cadence Design Systems, Inc. in San Jose is seeking a Senior Principal Digital Design Engineer to lead the design, development, and support of system-level memory IP models used in hardware-based verification products.
You will work across LPDDR, HBM, NAND Flash, eMMC, SD Card, DFI, and UFS, delivering high-quality RTL and verification solutions while collaborating with internal teams and external customers.
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