Lead Post-Silicon DVT Engineer for High-Speed ASICs

Posted yesterday

celero communicationsIrvine (CA)

Computer Hardware Engineers Semiconductor and Related Device Manufacturing

SENIORITY

Lead

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About the role

Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer in Irvine, CA to spearhead post-silicon validation for next-generation coherent DSP ASICs enabling AI and hyperscale networking. You will drive silicon characterization, enable first silicon bring-up, and build validation infrastructure while collaborating across Architecture, RTL, Firmware, Systems, and Customer Engineering. Strong leadership and a strategic validation mindset are required.

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