Lead Physical Design Engineers
digicomm semiconductorAustin (TX)
About the role
Analyze the design and divide into small blocks.
Split the circuit such that the number of connections between partitions is minimized.
Based on the design analysis identifying appropriate place for different blocks within the chip area.
Allocating places for external Hard IPs.
Placing and optimizing the various small blocks identified during partitioning process:
Post Placement Optimization (PPO) before clock tree synthesis (CTS)
Routing the various clock signals within the design so that the clock skews are optimized:
Clock Tree Synthesis (CTS)
Perform the STA, across the complete design to ensure that all the timing checks are clean:
Constraint Generation
Budgeting
Timing Sign off, IR/EM Analysis
Signal integrity
Perform Physical Verification against various critical parameters & criteria:
Layout Vs Schematic Checks (LVS)
Design Rule Checks (DRC)
Electrical Rule Checks (ERC)
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
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