Skip to main content
David Careers

Design Verification Engineer: SystemVerilog/UVM & SoCs

Posted 10 days ago

amazonAustin (TX)
Validation EngineersEngineering Services

SENIORITY

Lead

SALARY

$136,000 to $184,000 annually

Apply (opens in a new tab)

About the role

Amazon in Austin, Texas is seeking a Design Verification Engineer to ensure hardware and software solutions meet functionality standards. Responsibilities include developing comprehensive verification plans and measuring team metrics. Ideal candidates should have a Bachelor's degree in Electrical Engineering or a related field, along with over 3 years of experience in design verification using System Verilog and UVM. Competitive salary ranging from $136,000 to $184,000 annually, alongside substantial benefits including health insurance, parental leave, and retirement plans.

Before you apply

Applying takes about a minute. These four things decide how fast it moves after that.

Your profile is current

It's what we read first. Occupations, seniority and locations matter more than a long history.

Two examples you can talk through

Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.

A number in mind

What you're on now and what would make you move. We negotiate better when we know both.

Your notice period

Employers plan around it, and it's the question that stalls offers most often.

Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.

More like this