Senior ASIC Design Engineer - ML/Video Acceleration, Equity
metaAustin (TX)
Senior ASIC Design Engineer - ML/Video Acceleration, Equity
Posted today
metaAustin (TX)
SENIORITY
Manager
About the role
Meta is hiring ASIC Design Engineers to build cutting-edge ASICs for ML, video transcoding, and network acceleration. The role focuses on architecture exploration, micro-architecture development, and IP identification and integration with verification and emulation teams. Strong RTL skills in Verilog/System Verilog and HLS are required. Experience with SoC architectures and expertise in timing closure are highly valued.
Before you apply
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Your profile is current
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Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.