AI-Driven ASIC Intern: Silicon Performance & Safety
rivianPalo Alto (CA)
AI-Driven ASIC Intern: Silicon Performance & Safety
Posted 4 days ago
rivianPalo Alto (CA)
Computer Hardware EngineersResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)
SENIORITY
Intern
About the role
Rivian is seeking interns for its Spring Co-op program in Palo Alto, CA. You must be an undergraduate or graduate student with an expected graduation date between December 2027 and 2029 and available for the full spring term.
In this role you will evaluate AI tools for Silicon development, build C++/SystemC performance models, and create verification assets for ASICs in ISO 26262 compliant ADAS contexts.
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
More like this