High-Speed Hardware Engineer — PCIe Gen5 & Failure Analysis

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realignSan Jose (CA)

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About the role

Realign Llc in San Jose, CA is seeking an experienced Hardware Engineer to lead high-speed complex hardware design and failure analysis. You will work on networking products with SERDES >25G, PCIe Gen 5+, DDR5 and NVMe/PCIe interfaces, and contribute to power supply architectures. You will perform board bring-up, hardware validation, and qualification testing. Candidates should have 8+ years of hands-on hardware design experience, Cadence CAD workflows, and strong SI/PI skills.

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