Senior ASIC Physical Design Engineer

The Senior ASIC Physical Design Engineer leads implementation of assigned SoC partitions, focusing on synthesis, place and route, and static timing closure. Working on-site with design, DFT, and architecture teams, this role resolves implementation and signoff issues, manages EM/IR, PDN, LEC, and physical verification for sub-7nm technologies, and refines PD methodologies and custom TCL-based flows while collaborating with EDA vendors to troubleshoot and improve design flows. Execute synthesis, PnR, and STA for assigned ASIC/SoC partitions to meet performance, area, and power goals. Collaborate with architects, RTL, and DFT engineers to resolve implementation and signoff issues across design blocks. Close EM/IR, manage PDN-related tasks, and drive LEC and physical verification signoff for owned partitions. Identify and address physical design challenges early to enable efficient design iteration and convergence. Contribute to improving PD flows and methodologies, including synthesis, PnR, EMIR, PDN, and LEC. Troubleshoot design and flow issues, working with EDA vendors to resolve tool or methodology problems. Apply low-power design techniques within the physical implementation flow for advanced process nodes. ASIC physical design Synthesis (logic) Place and route (PnR) Static timing analysis (STA) EM/IR and power integrity EDA tools: Innovus/Tempus/Quantus System-on-Chip (SoC) implementation TCL scripting for EDA flows Physical verification & LEC Low-power design techniques Medical Insurance Dental Insurance Vision Insurance 401k