Senior ASIC Physical Design Lead, RTL-to-GDSII
cisco systemsAustin (TX)
Senior ASIC Physical Design Lead, RTL-to-GDSII
Posted today
cisco systemsAustin (TX)
SENIORITY
Lead
About the role
Cisco Systems, Inc. is seeking an experienced Physical Design Engineer to own RTL-to-GDSII flows for advanced node tapeouts. You will work across RTL, DFT, and implementation teams to optimize performance and die size on cutting-edge silicon.
Ideal candidates have extensive full-chip experience, CTS leadership, and strong scripting in Python, TCL, or Perl. This role is on-site in the Austin area with Cisco’s Global Hardware Engineering team.
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