Senior Analog Timing Designer – High-Performance ICs
ipro networks pteTempe (AZ)
Senior Analog Timing Designer – High-Performance ICs
Posted yesterday
ipro networks pteTempe (AZ)
SENIORITY
Senior
About the role
Intellipro in Tempe, AZ is seeking an Analog Designer – Timing to join the timing product development team for high-performance networking and data center applications. This full-time, on-site role offers the chance to work on novel timing products with a talented team.
You will design mixed-signal modules, contribute from definition to release, and mentor layout engineers. A MSEE with 3+ years and hands-on Cadence Spectre/AMS experience are required; knowledge of PLL, phase noise, and 65nm CMOS
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