Principal PE Validation Engineer — Memory Interface

Posted today

rambuscomSan Jose (CA)

Validation Engineers Electronic Computer Manufacturing

SENIORITY

Lead

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About the role

Rambus seeks a Principal Validation Engineer for its Memory Interface Chip unit in California. The role focuses on lab bring-up, validating high-speed memory designs, and developing automated scripts for lab data analysis. Strong memory system and high-speed signaling knowledge are required, with hands-on hardware experience including x86 systems. The position is full-time with hybrid work options, offering base salary, bonus, equity, and benefits.

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