Design Verification Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: As a Design Verification Engineer Lead in the AECG Group, you will help bring to life cutting‑edge FPGA and ASIC solutions for a broad range of customers. As a member of the front‑end design and integration team, you will collaborate closely with architecture, IP design, physical design, firmware, and product engineering teams to deliver first‑pass silicon success for next‑generation PCIe and CXL‑based IP solutions. THE PERSON: You are passionate about complex IP architectures, digital design, and advanced verification methodologies. You thrive in a collaborative environment, enjoy solving challenging technical problems, and have a proven ability to work effectively across global teams. You bring strong analytical skills, technical leadership, and a continuous learning mindset. KEY RESPONSIBILITIES: Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high‑speed connectivity features. Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system‑level use cases. Design and implement IP or subsystem‑level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components. Develop directed and constrained‑random tests, execute regressions, and debug failures to ensure high functional coverage and design quality. Drive verification automation, methodology improvements, and adoption of AI‑assisted tools to improve development efficiency and productivity. PREFERRED EXPERIENCE: ASIC/IP verification experience using UVM methodology. Strong expertise in SystemVerilog, Verilog, object‑oriented programming, and UVM‑based verification environments. Experience verifying high‑speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet. Proficiency in scripting and automation using Python, Perl, or similar languages. Experience working across the ASIC/FPGA development lifecycle from planning through tape‑out. Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements. Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams. Knowledge of computer architecture, system‑level design concepts, and emerging AI‑driven verification methodologies is a plus. ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Minimum 10 years of design verification experience using UVM methodology. LOCATION: San Jose, CA This role is not eligible for visa sponsorship. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. This posting is for an existing vacancy. #J-18808-Ljbffr