Principal Digital Verification Engineer - ASIC / UVM
usa tech recruitGates (NY)
Principal Digital Verification Engineer - ASIC / UVM
Posted yesterday
usa tech recruitGates (NY)
SENIORITY
Lead
About the role
Principal Digital Verification Engineer - ASIC / UVM Have you got what it takes to succeed The following information should be read carefully by all candidates. We are currently partnered with a leading networking and telecommunications technology company looking to expand their team with a Principal Digital Verification Engineer to drive verification strategies for next-generation products. This is a permanent position, based near Rochester, New York. Key responsibilities for this Principal Digital Verification Engineer position: Analyse project architecture and functional requirements in collaboration with systems engineers and architects. Validate digital subsystems using simulation, formal verification, and coverage methodologies. Create, review, and optimise simulation environments, test scenarios, functional coverage plans, and formal verification test plans. Lead focused technical initiatives and mentor team members as required. Direct verification activities as an ASIC Verification Prime when assigned. Participate in architectural and design reviews to identify verification impacts and coverage opportunities.
Key requirements:
12+ years of digital verification experience using SystemVerilog, UVM, SVA, and major vendor simulators. Proven ability to define and execute comprehensive digital verification and coverage strategies. Strong debugging skills with a methodical approach to complex technical problems. Experience with formal verification methods advantageous. Familiarity with DSP and/or Forward Error Correction (FEC) technologies a plus. Experience with Python, C/C++, Git, and Jira desirable. xuwmhxw Keywords: Digital Verification / ASIC Verification / UVM / SystemVerilog / SVA / Formal Verification / Coverage / Digital Verification / Optical Networking / DSP / FEC / Telecommunications / Python / C / C++ / Git If you are interested in this Principal Digital Verification Engineer position, please send a copy of your CV to By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice
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