Advanced-Node SoC Physical Design Lead (7/5/3nm)
sk hynix memory solutionsSan Jose (CA)
Advanced-Node SoC Physical Design Lead (7/5/3nm)
Posted yesterday
sk hynix memory solutionsSan Jose (CA)
SENIORITY
Lead
About the role
SK hynix memory solutions in San Jose seeks a Sr. Staff / Principal Physical Design Engineer to lead high-performance SoC physical implementation from RTL to GDS. You will work closely with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success.
You will mentor junior engineers, define team methodologies, and drive tapeouts across 7nm/5nm/3nm nodes, balancing performance, power, and area in a fast-paced environment.
Before you apply
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Your profile is current
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Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
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Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
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