Senior ASIC Design Engineer - Video IP RTL Architect
trilinearPortland (ME)
Senior ASIC Design Engineer - Video IP RTL Architect
Posted yesterday
trilinearPortland (ME)
SENIORITY
Senior
About the role
Trilinear Technologies in Portland, OR is seeking an experienced RTL engineer to contribute to the next generation of IP products. You will develop high-quality RTL and SystemVerilog code while collaborating with customers to integrate our designs into their architectures.
The ideal candidate will have:
5+ years in RTL development, strong Verilog/SystemVerilog experience, and a proven track record of delivering reliable IP.
Before you apply
Applying takes about a minute. These four things decide how fast it moves after that.
Your profile is current
It's what we read first. Occupations, seniority and locations matter more than a long history.
Two examples you can talk through
Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.
A number in mind
What you're on now and what would make you move. We negotiate better when we know both.
Your notice period
Employers plan around it, and it's the question that stalls offers most often.
Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.
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